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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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NAU8502YG Fiches technique(PDF) 39 Page - Nuvoton Technology Corporation |
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NAU8502YG Fiches technique(HTML) 39 Page - Nuvoton Technology Corporation |
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39 / 92 page  NAU8502 emPowerAudio ™ Datasheet Revision 2.5 Page 39 of 92 March, 2014 Separate from this ADC clock subsystem, audio data are clocked to and from the 8502 by means of the control logic described in the Digital Audio Interfaces section. The Frame Sync (FS) and Bit Clock (BCLK) pins in the Digital Audio Interface manage the audio bit rate and audio sample rate for this data flow. It is important to understand that the Digital Audio Interface does not determine the sampling rate for the ADC data converters, and instead, this rate is derived exclusively from the Internal Master Clock (IMCLK). It is therefore a requirement that the Digital Audio Interface and data converters be operated synchronously, and that the FS, BCLK, and IMCLK signals are all derived from a common reference frequency. If these three clock signals are not synchronous, audio quality will be reduced. The IMCLK is always exactly 256 times the sampling rate of the data converters. IMCLK is output from the Master Clock Prescaler. The prescaler reduces by an integer division factor the input frequency input clock. The source of this input frequency clock is either the external MCLK pin, or the output from the internal PLL Block. In Master Mode, the IMCLK signal is used to generate FS and BCLK signals that are driven onto the FS and BCLK pins and input to the Digital Audio Interface. FS is always IMCLK/256 and the duty cycle of FS is automatically adjusted to be correct for the mode selected in the Digital Audio Interface. The frequency of BCLK may optionally be divided to optimize the bit clock rate for the application scenario. In Slave Mode, there is no connection between IMCLK and the FS and BCLK pins. In this mode, FS and BCLK are strictly input pins, and it is the responsibility of the system designer to ensure that FS, BCLK, and IMCLK are synchronous and scaled appropriately for the application. Addr D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x07 SDODIS MS FSP WLEN FORMAT 0A 0x26 CLKM MCLKSEL[2:0] BCLKSEL[2:0] PLLEN 0x140 0x27 SMPLR[3:1] SLOWCLKEN 0x000 0x44 PLLMCLK PLLN_A[3:0] 0x008 0x45 PLLK_A[23:18] 0x00C 0x46 PLLK_A[17:9] 0x093 0x47 PLLK_A[8:0] 0x0E9 0x44 PLLREGSEL PLLMCLK PLLN_B[3:0] 0x008 0x45 PLLK_B[23:18] 0x00C 0x46 PLLK_B[17:9] 0x093 0x47 PLLK_B[8:0] 0x0E9 Table 20: Registers associated with PLL 11.9.1 Phase Locked Loop (PLL) General Description The PLL may be optionally used to multiply an external input clock reference frequency by a high resolution fractional number. To enable the use of the widest possible range of external reference clocks, the PLL block |
Numéro de pièce similaire - NAU8502YG |
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Description similaire - NAU8502YG |
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