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M58-ZC Fiches technique(PDF) 21 Page - Nuvoton Technology Corporation |
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M58-ZC Fiches technique(HTML) 21 Page - Nuvoton Technology Corporation |
21 / 71 page NuMicro ™ M058/M0516BN Datasheet Publication Release Date: Mar. 19, 2012 - 21 - Revision V1.01 6 FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex™-M0 Core The Cortex ™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB- Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor. The profile supports two modes -Thread and Handler modes. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. Cortex-M0 Processor Core Nested Vectored Interrupt Controller (NVIC) Breakpoint and Watchpoint Unit Debugger interface Bus matrix Debug Access Port (DAP) Debug Cortex-M0 processor Cortex-M0 components Wakeup Interrupt Controller (WIC) Interrupts Serial Wire or JTAG debug port AHB-Lite interface Figure 6-1 Functional Block Diagram The implemented device provides: A low gate count processor the features: The ARMv6-M Thumb ® instruction set. Thumb-2 technology. ARMv6-M compliant 24-bit SysTick timer. A 32-bit hardware multiplier. The system interface supports little-endian data accesses. The ability to have deterministic, fixed-latency, interrupt handling. |
Numéro de pièce similaire - M58-ZC |
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Description similaire - M58-ZC |
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