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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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N681387DG Fiches technique(PDF) 69 Page - Nuvoton Technology Corporation |
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N681387DG Fiches technique(HTML) 69 Page - Nuvoton Technology Corporation |
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69 / 164 page  N681386/87 Single Programmable Extended Codec/SLCC Preliminary Datasheet Rev1.0 Page 69 of 164 January 2010 Bit Location Bit Description Bit Name Bit Value 0 1 1 Control bit to select 12-Bits monitoring XP Bits[11-4] Bits[3-0] 2 This is a channel selection bit. In case of a single channel device this bit must be set to “0” CH 0 NA 3 - 6 Must be set to “0” for all operation - - - 7 Read/Write control bit RW Write Read CH XP Command 0 0 Register Address (8-bits) 0 1 2 nd byte of 12-Bits monitoring Table 32: 12-bit byte Selection 12.2.4. READ/WRITE SEQUENCE (8-BIT OR 16-BIT) The device is accessed via the SDI input with data clocked in on the rising edge of SCLK. DATA transfer is synchronized to the SCLK input. Data is clocked out onto SDO on the falling edges of SCLK. SCLK is the only reference of SDI and SDO pins. The SDO pin will go tri-state when goes CSb HIGH The first two pictures below illustrate the Read/Write Sequence for an 8-bit architecture. Both Read/Write sequences consist of three 8-bit transmissions, Device address, Register Address and Data. Each 8-bit transmission starts with the falling edge of the CSb line. At the end of every 8-bit transmission is complete the CSb transitions from LOW back to HIGH. After a valid Device Address and Register Address for Read, 8-bit Data is shifted out on the SDO line. The last two pictures below illustrate the Read/Write Sequence for a 16-bit architecture. Both Read/Write sequences consist of two 16-bit transmissions, the first 16-bit transmission consisting of Device address and Register Address bytes and the second 16-bit transmission consists of Data. Each 16-bit transmission starts with the falling edge of the CSb line. At the end of every 16-bit transmission CSb transitions from LOW back to HIGH. After a valid Device address and Register Address for Read, 16-bits of Data is shifted out on the SDO line. Since all the registers are 8- bits long, the least significant byte of the 16-bit Data word should be ignored. If additional clocks are sent by the master the device will provide the same data when BST is LOW. The SPI state machine soft resets whenever CSb asserts during an operation on an SCLK cycle that is not a multiple of eight, including burst mode. This is a mechanism for the controller to force the state machine to a known state when the controller and the device are out of synchronization. |
Numéro de pièce similaire - N681387DG |
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Description similaire - N681387DG |
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