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M54-LN Datasheet(Fiches technique) 43 Page - Nuvoton Technology Corporation

Numéro de pièce M54-LN
Description  32-BIT MICROCONTROLLER
Télécharger  71 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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NuMicro
M058/M0516 Data Sheet
Publication Release Date: May 30, 2011
- 43 -
Revision V2.00
6.9 Watchdog Timer (WDT)
6.9.1
Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports another function to wakeup chip from power down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals. Table 6-2 show the
watchdog timeout interval selection and Figure 6.9-1 shows the timing of watchdog interrupt
signal and reset signal.
Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up.
When the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will
be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is
set, in the meanwhile, a specified delay time (1024 * TWDT) follows the time-out event. User must
set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid chip
from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by
hardware after WDT counter is reset. There are eight time-out intervals with specific delay time
which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (WTRF) high and reset chip. This reset will last 63 WDT clocks (TRST)
then chip restarts executing program from reset vector (0x0000 0000). WTRF will not be cleared
by Watchdog reset. User may poll WTFR by software to recognize the reset source. WDT also
provides wakeup function. When chip is powered down and the Watchdog Timer Wake-up
Function Enable bit (WDTR[4]) is set, if the WDT counter reaches the specific time interval
defined by WTIS (WDTCR [10:8]) , the chip is waken up from power down state. First example, if
WTIS is set as 000, the specific time interval for chip to wake up from power down state is 2
4 *
TWDT. When power down command is set by software, then, chip enters power down state. After
2
4 * T
WDT time is elapsed, chip is waken up from power down state. Second example, if WTIS
(WDTCR [10:8]) is set as 111, the specific time interval for chip to wake up from power down
state is 2
18 * T
WDT. If power down command is set by software, then, chip enters power down
state. After 2
18 * T
WDT time is elapsed, chip is waken up from power down state. Notice if WTRE
(WDTCR [1]) is set to 1, after chip is waken up, software should chip the Watchdog Timer counter
by setting WTR(WDTCR [0]) to 1 as soon as possible. Otherwise, if the Watchdog Timer counter
is not cleared by setting WTR (WDTCR [0]) to 1 before time starting from waking up to software
clearing Watchdog Timer counter is over 1024 * TWDT , the chip is reset by Watchdog Timer.
WTIS
Timeout Interval Selection
TTIS
Interrupt Period
TINT
WTR Timeout Interval (WDT_CLK=10 kHz)
MIN. TWTR ~ MAX. TWTR
000
2
4 * TWDT
1024 * TWDT
1.6 ms ~ 104 ms
001
2
6 * TWDT
1024 * TWDT
6.4 ms ~ 108.8 ms
010
2
8 * TWDT
1024 * TWDT
25.6 ms ~ 128 ms
011
2
10 * TWDT
1024 * TWDT
102.4 ms ~ 204.8 ms
100
2
12 * TWDT
1024 * TWDT
409.6 ms ~ 512 ms




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