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N681386 Fiches technique(PDF) 98 Page - Nuvoton Technology Corporation |
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N681386 Fiches technique(HTML) 98 Page - Nuvoton Technology Corporation |
98 / 164 page N681386/87 Single Programmable Extended Codec/SLCC Preliminary Datasheet Rev1.0 Page 98 of 164 January 2010 14.5.5. INTERRUPT ENABLE REGISTER 2 Addr. Name D7 D6 D5 D4 D3 D2 D1 D0 Default 0x29 IE2 FSKIE DTMFIE RIE RAE O2IE O2AE O1IE O1AE 0x00 Bit Location Bit Description Bit Name Bit Value 0 1 0 Oscillator 1 Active Timer O1AE Masked Enabled 1 Oscillator 1 Inactive Timer O1IE Masked Enabled 2 Oscillator 2 Active Timer O2AE Masked Enabled 3 Oscillator 2 Inactive Timer O2IE Masked Enabled 4 Ringing Active Timer RAE Masked Enabled 5 Ringing Inactive Timer RIE Masked Enabled 6 DTMF Inactive Timer DTMFIE Masked Enabled 7 FSK Enable FSKIE Masked Enabled 14.5.6. INTERRUPT STATUS REGISTER 3 Addr. Name D7 D6 D5 D4 D3 D2 D1 D0 Default 0x2A INT3 RES GKDI RES TMP 0x00 “RES” in the register map means reserved bit(s). This register displays the status of the dice Temperature interrupt of the device. A pending interrupt is represented by a HIGH “1” in the respective bit. Writing 1 to that respective bit clears the pending interrupt. Bit Location Bit Description Bit Name Bit Value 0 1 0 Die Temperature Interrupt TMP No INT INT Pending 3 Ground Key Detection Interrupt GKDI No INT INT Pending |
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