Moteur de recherche de fiches techniques de composants électroniques |
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I5102EY Fiches technique(PDF) 26 Page - Nuvoton Technology Corporation |
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I5102EY Fiches technique(HTML) 26 Page - Nuvoton Technology Corporation |
26 / 90 page ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 26 - Revision 1.42 4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE. 7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. To set up the chip for Memo Record, the configuration registers are set up as follows: CFG0=0010 0100 0010 0001 (hex 2421). CFG1=0000 0001 0100 1000 (hex 0148). Only those portions necessary for this mode are powered up. 6.3.10 Memo and Call Playback This mode sets the chip up for local playback of messages recorded earlier. The playback path is from the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be powered down. 1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0, the state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL STORAGE ARRAY. 2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO. 4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. |
Numéro de pièce similaire - I5102EY |
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Description similaire - I5102EY |
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