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TPS51020DBTRG4 Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS51020DBTRG4 Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 27 page TPS51020 SLUS564B − JULY 2003 − REVISED DECEMBER 2003 11 www.ti.com APPLICATION INFORMATION SKIP MODE OPERATION If the SKIP pin is set HIGH, the SMPS operates in the fixed PWM mode. While a LOW signal is applied, the controller operates in autoskip mode. In the autoskip mode, the operation changes from constant frequency PWM mode to an energy-saving skip mode automatically by detecting the edge of discontinuous current mode. During the skip mode, the hysteretic comparator monitors output voltage to trigger high side on at the next coming oscillator pulse after the lower level is detected. Several sequential pulses may be seen, especially in the intermediate load level, before output capacitor is charged up to the higher level and waits for next cycle. In the skip mode, frequency varies with load current and input voltage. Skip mode for SMPS_2 is disabled regardless of the SKIP pin status if DDR mode is selected (see Dual Mode and DDR Mode section). This is because current sink capability is required for VTT, so that rectifying MOSFET needs to be kept on when the inductor current flows inversely. SMPS_1 is still capable of skip mode operation while DDR Mode. CASCADE CONFIGURATION If the TRIP2 pin is tied through a resistor to the input voltage, the TPS51020 assumes that the conversion voltage for channel two is the VIN voltage, usually VBATT. Conversely, if TRIP2 is tied through a resistor to ground, the controller assumes that the conversion voltage for channel two is the output voltage of channel one or some other stable bus voltage. DUAL MODE AND DDR MODE TPS51020 provides one-chip solution for system power supply, such as for 5 V, 3.3 V or 1.8 V, and a dual switcher DDR power supply. By simply selecting DDR signal and some external configuration change following the instructions below, TPS51020 gives a complete function set required for the DDR termination supply such as VDDQ/2 tracking VTT source/sink capability and VTT reference output. If DDR is set high ( > 2.2 V), the TPS51020 runs in dual mode, that is, each converter produces an independent output voltage with respect to the internal 0.85-V reference. Bypass REF_X to ground by 0.01- µF. The VO1_VDDQ or VO2 terminal can be connected to either to their corresponding switcher output or ground, depending on customer’s choice of using or not using the output discharge function (See Softstop). The 10-V reference output can be used as FET switch biasing for power control during sleep states (see Figure 5). During this dual mode, selection of autoskip mode or PWM mode made by SKIP applies to both SMPS_1 and SMPS_2. If DDR is set low ( < 0.3V), the TPS51020 operates as a dual switcher DDR supply; VDDQ from SMPS_1 and VTT from SMPS_2 (DDR Mode). In this mode, the reference voltage for SMPS_2 is switched to (VO1_VDDQ)/2 to track exactly half the voltage of SMPS_1, divided by internal resistors. VO1_VDDQ should be connected to SMPS_1 output terminal to accomplish this, while VO2 connection is still flexible to the customer’s choice of softstop. REF_X outputs the (VO1_VDDQ)/2 voltage after a buffer (5-mA max). SKIP controls only SMPS_1 and SMPS_2 is forced to operate in PWM mode so that current can be sink from the output. Power source of SMPS_2 can either be the battery voltage (independent configuration), or the VDDQ (cascade configuration) by user’s preference. When using the independent configuration, TRIP2 needs to be connected to the VIN node via trip resistor. In case of cascade configuration, tie TRIP2 to GND via trip resistor (see Figure 7). CAUTION:Do NOT toggle DDR HIGH while ENBL1 or ENBL2 is high (see Table 2). REF_X output switches to high voltage (10 V) and be applied to VTTREF directly |
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