TPS51020

SLUS564B − JULY 2003 − REVISED DECEMBER 2003

8

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

PGOOD

12

O

both outputs become within

±7.5%. If INV1 or INV2 is out of regulation, or VREG5V goes under UVLO then this

ENBLx is low, and the power good output is high, then the power good signal for that channel is ignored.

REF_X

8

O

10-V N-channel MOSFET bias or (VO1_VDDQ)/2 reference output. If dual mode is selected (DDR > 2.2 V)

then this pin provides a low 10-V current (< 2 mA) bias, dropped down from VIN, for the SO – S5 switched

of 3 mA source current. This bias/reference is shut off when ENBL1 and ENBL2 are both low. (See Table 2)

REG5_IN

21

I

External 5V regulator Input. If this pin is above 4.7 V, then the 5 V circuit bias switches from the VREF5 to the

supply presented to REG5_IN.

SSTRT1

3

I

Soft-start/frequency select input. Connect a capacitor between SSTRTx and ground for adjusting the softstart

SSTRT2

13

I

scribed in Table 1. The soft-start capacitor is discharged upon UVLO/OVP/UVP, or when ENBLx is asserted

low.

SKIP

4

I

Skip mode selection pin. Ground for automatic control between PWM mode in heavy load and hysteretic op-

eration in light load. Tie high for PWM only operation for the entire load condition. If DDR is grounded, then skip

mode is disabled for Channel 2.

TRIP1

25

I

Channel 1 overcurrent trip point voltage input. Connect a resistor between TRIP1 and the high-side N-channel

MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down. Connect

resistor between TRIP1 and GND for low-side N-channel MOSFET overcurrent latch shutdown.

TRIP2

23

I

Channel 2 overcurrent trip point voltage input. Connect a resistor between TRIP2 and the high-side N-channel

MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down with a 180

°

channel phase shift. Connect resistor between TRIP2 and GND for low-side N-channel MOSFET over current

when this pin is tied to ground via a resistor.

VBST1

30

I

Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.

VBST2

16

I

Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.

VO1_VDDQ

5

I

not required. When grounded, corresponding channel disables the low side N-channel MOSFET during start-

VO2

11

I

not required. When grounded, corresponding channel disables the low side N-channel MOSFET during start-

nected to the VDDQ output since this pin works as the VDDQ feedback to generate the VTT reference voltage

and VO2 should be connected to GND since VTT must remain in a high-impedance state during S3 mode.

VREG5

22

O

Internal, 60-mA, 5-V regulator output. DDR, ENBL1 or ENBL2 high ( > 2.2V) turns on the 5 V regulator.

VIN

24

I

pin and the high-side N-channel MOSFET drain where positive node of TRIPx resistors are located.

Table 2. Reference Regulator Control

MODE

DDR

ENBL1

ENBL2

VREF5

REF_X

OSC

DDR

LOW

LOW

LOW

OFF

OFF

OFF

DDR

LOW

LOW

HIGH

ON

OFF

ON

DDR

LOW

HIGH

LOW

ON

VO1_DDR

2

ON

DDR

LOW

HIGH

HIGH

ON

VO1_DDR

2

ON

DUAL

HIGH

LOW

LOW

ON

OFF

OFF

DUAL

HIGH

LOW

HIGH

ON

10 V

ON

DUAL

HIGH

HIGH

LOW

ON

10 V

ON

DUAL

HIGH

HIGH

HIGH

ON

10 V

ON