Preliminary
GS832218(B/E)/GS832236(B/E)/GS832272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06 9/2004
3/41
© 2001, GSI Technology
GS832272 209-Bump BGA Pin Description
Symbol
Type
Description
A0, A1
I
Address field LSBs and Address Counter Preset Inputs.
An
I
Address Inputs
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O
Data Input and Output pins
BA, BB
I
Byte Write Enable for DQA, DQB I/Os; active low
BC,BD
I
Byte Write Enable for DQC, DQD I/Os; active low
BE, BF, BG,BH
I
Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
NC
—
No Connect
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
SCD
I
Single Cycle Deselect/Dual Cycle Deselect Mode Control
MCH
I
Must Connect High
MCL
Must Connect Low
BW
I
Byte Enable; active low
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock