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MVTX2603AG Fiches technique(PDF) 10 Page - Zarlink Semiconductor Inc

No de pièce MVTX2603AG
Description  Unmanaged 24-Port 10/100 Mb 2-Port 1 Gb Ethernet Switch
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Fabricant  ZARLINK [Zarlink Semiconductor Inc]
Site Internet  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

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MVTX2603
Data Sheet
10
Zarlink Semiconductor Inc.
1.0
Block Functionality
1.1
Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined synchronrous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non-
blocking switch, two memory domains are required. Each domain has a 64 bit wide memory bus. At 100 MHz, the
aggregate memory bandwidth is 12.8 Gbps, which is enough to support 24 10/100 Mbps and 2 Gigabit ports at full
wire speed switching. For 24+ 2 stacking application, ZBT memory at 125 MHz is required.
The Switching Database is also located in the external SBRAM; it is used for storing MAC addresses and their
physical port number. It is duplicated and stored in both memory domains. Therefore, when the system updates the
contents of the switching database, it has to write the entry to both domains at the same time.
1.2
GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between
the Frame Engine (FE) and the external physical device (PHY).
The MVTX2603 GMAC implements both GMII and MII interfaces, which offers a simple migration from 10/100 to
1 G. The GMAC of the MVTX2603 meets the IEEE 802.3Z specification. It is able to operate in 10 M/100 M either
Half or Full Duplex mode with a back pressure/flow control mechanism or in 1 G full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. PHY
addresses for GMAC are 01h and 02h.
1.3
Physical Coding Sublayer (PCI) Interface
For the MVTX2603, the 1000BASE-X PCI Interface is designed internally and may be utilized in the absence of a
GMII. The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to
(from) 8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex
mode. It also manages the Auto negotiation process by informing the management entity that the PHY is ready for
communications. The on-chip TBI may be disabled if TBI exists within the Gigabit PHY. The TBI interface provides
a uniform interface for all 1000 Mbps PHY implementations.
The PCS comprises the PCS Transmit, Synchronization, PCS Receive and Auto negotiation processes for
1000BASE-X.
The PCS Transmit process sends the TBI signals TXD [9:0] to the physical medium and generates the GMII
Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission.
Additionally, the Transmit process generates an internal “transmitting” flag and monitors Auto negotiation to
determine whether to transmit data or to reconfigure the link.
The PCS Synchronization process determines whether or not the receive channel is operational.
The PCS Receive process generates RXD [7:0] on the GMII from the TBI data [9:0], and the internal “receiving” flag
for use by the Transmit processes.
The PCS Auto negotiation process allows the MVTX2603 to exchange configuration information between two
devices that share a link segment and to automatically configure the link for the appropriate speed of operation for
both devices.
1.4
10/100 MAC Module (RMAC)
The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame
Engine (FE) and the external physical device (PHY). The MVTX2603 has two interfaces, RMII or Serial (only for
10 M). The 10/100 MAC of the MVTX2603 device meets the IEEE 802.3 specification. It is able to operate in either
Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit
upon collision for up to 16 total transmissions. The PHY address for 24 10/100 MAC are from 08h to 1fh.


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