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CD54HCT283F3A Fiches technique(PDF) 1 Page - Texas Instruments |
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CD54HCT283F3A Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 11 page 1 Data sheet acquired from Harris Semiconductor SCHS176D Features • Adds Two Binary Numbers • Full Internal Lookahead • Fast Ripple Carry for Economical Expansion • Operates with Both Positive and Negative Logic • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC283 and ’HCT283 binary full adders add two 4-bit binary numbers and generate a carry-out bit if the sum exceeds 15. Because of the symmetry of the add function, this device can be used with either all active-high operands (positive logic) or with all active-low operands (negative logic). When using positive logic the carry-in input must be tied low if there is no carry-in. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC283F3A -55 to 125 16 Ld CERDIP CD54HCT283F3A -55 to 125 16 Ld CERDIP CD74HC283E -55 to 125 16 Ld PDIP CD74HC283M -55 to 125 16 Ld SOIC CD74HC283MT -55 to 125 16 Ld SOIC CD74HC283M96 -55 to 125 16 Ld SOIC CD74HCT283E -55 to 125 16 Ld PDIP CD74HCT283M -55 to 125 16 Ld SOIC CD74HCT283MT -55 to 125 16 Ld SOIC CD74HCT283M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC283, CD54HCT283 (CERDIP) CD74HC283, CD74HCT283 (PDIP, SOIC) TOP VIEW Functional Diagram 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 S1 B1 A1 S0 A0 B0 GND CIN VCC A2 S2 A3 B3 S3 COUT B2 5 6 3 2 15 11 12 14 4 9 S2 S1 A0 B0 A1 B1 B2 A3 B3 A2 7 CIN GND = 8 VCC = 16 10 13 1 S0 S3 COUT November 1997 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry [ /Title (CD74 HC283 , CD74 HCT28 3) /Sub- ject (High Speed CMOS Logic 4-Bit Binary Full Adder |
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