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AD9554-1 Fiches technique(PDF) 50 Page - Analog Devices

No de pièce AD9554-1
Description  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9554-1 Fiches technique(HTML) 50 Page - Analog Devices

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AD9554-1
Data Sheet
Rev. C | Page 50 of 99
PROGRAMMING THE I/O REGISTERS
The register map (see Table 31) spans an address range from
0x0000 through 0x1788. Each address provides access to one byte
(eight bits) of data. Each individual register is identified by its
four digit hexadecimal address (for example, Register 0x0A23).
In some cases, a group of addresses collectively defines a register.
In general, when a group of registers defines a control parameter,
the LSB of the value resides in the D0 position of the register
with the lowest address. The bit weight increases right to left,
from the lowest register address to the highest register address.
BUFFERED/ACTIVE REGISTERS
There are two copies of most registers: buffered and active. The
value in the active registers is the one that is in use. The buffered
registers are the ones that take effect the next time the user writes
0x01 to Register 0x000F (IO_UPDATE). Buffering the registers
allows the user to update a group of registers (like the APLL
settings) simultaneously, avoiding the potential of unpredictable
behavior in the device. Registers with an L in the option column
of the register map (see Table 31) are live, meaning that they
take effect the moment the serial port transfers that data byte.
WRITE DETECT REGISTERS
A Wx (where x equals 1 to 8) in the option column of the
register map (see Table 31) identifies a register with write
detection. These registers contain additional logic to avoid
glitches or unwanted operation.
Table 29. Register Write Detection Description
Option
Register Operation
W1
When these registers are written to, the lock detector
immediately declares it is unlocked. The lock detection
restarts when the next IO_UPDATE occurs.
W2
After these registers are written to, the DPLL faults
the reference input and automatically enters holdover
for one PFD cycle (and then exits) when an
IO_UPDATE is issued. However, this action is only
performed if the written register belongs to the
actively selected reference.
W3
After these registers are written to, the DPLL lock
detector unlocks.
W5
The watchdog timer resets automatically when
these registers are written to and then resumes
counting on the next IO_UPDATE.
W6
The system clock stability timer is automatically
reset when these registers are changed and then
resumes counting on the next IO_UPDATE. (Note
that the SYSCLK stability timer starts only after the
system clock is locked.
W7
If these registers are written to while they are
assigned to an existing function, the existing
function stops immediately. The new function starts
when the next IO_UPDATE occurs.
W8
Almost identical to W2; however, the DPLL must be
in demapping mode.
AUTOCLEAR REGISTERS
An A in the option column of the register map (see
Table 31) identifies an autoclearing register. Typically, the active
value for an autoclearing register takes effect following an
IO_UPDATE. The bit is cleared by the internal device logic
upon completion of the prescribed action.
REGISTER ACCESS RESTRICTIONS
Read and write access to the register map may be restricted,
depending on the register in question, the source and direction
of access, and the current state of the device. Each register can
be classified into one or more access types. When more than
one type applies, the most restrictive condition is the one that
applies.
When access is denied to a register, all attempts to read the
register return a 0 byte, and all attempts to write to the register
are ignored. Access to nonexistent registers is handled in the
same way as for a denied register.
Regular Access
Registers with regular access do not fall into any other category.
Read Only Access
An R in the option column of the register map (see
Table 31) identifies read only registers. Serial port access is
available at all times.


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