N01L163WC2AT-55I datasheet(5/11 Pages) NANOAMP

No de pièce	N01L163WC2AT-55I

Description	1Mb Ultra-Low Power Asynchronous CMOS SRAM

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Fabricant	NANOAMP [NanoAmp Solutions, Inc.]

Site Internet	http://www.nanoamp.com

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5 / 11 page

(DOC# 14-02-010 REV F ECN# 01-0996)

5

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

NanoAmp Solutions, Inc.

N01L163WC2A

Power Savings with Page Mode Operation (WE = VIH)

Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal

organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power

saving feature.

The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open

and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant

bits and addressing the 16 words within the open page, power is reduced to the page mode value which is

considerably lower than standard operating currents for low power SRAMs.

Page Address (A4 - A15)

LB, UB

OE

CE1

CE2

Word Address (A0 - A3)

Open page

Word 1

Word 2

Word 16

...

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