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CXK79M36C162GB-5 Fiches technique(PDF) 10 Page - Sony Corporation

No de pièce CXK79M36C162GB-5
Description  18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
Download  25 Pages
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Fabricant  SONY [Sony Corporation]
Site Internet  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXK79M36C162GB-5 Fiches technique(HTML) 10 Page - Sony Corporation

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SONY®
ΣRAM
Preliminary
18Mb 1x2Lp, HSTL, rev 1.1
10 / 25
November 8, 2002
CXK79M36C162GB
AC Electrical Characteristics
(VDD =1.8V ± 0.1V, VSS =0V, TA =0 to 85
oC)
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted.
1. These parameters apply to control inputs E1, E2, E3, ADV, and W.
2. These parameters are guaranteed by design through extensive corner lot characterization.
3. These parameters are measured at
± 50mV from steady state voltage.
Parameter
Symbol
-33
-4
-5
Units
Notes
MinMax
MinMax
MinMax
Input Clock Cycle Time
tKHKH
3.3
---
4.0
---
5.0
---
ns
Input Clock High Pulse Width
tKHKL
1.3
---
1.5
---
2.0
---
ns
Input Clock Low Pulse Width
tKLKH
1.3
---
1.5
---
2.0
---
ns
Address Input Setup Time
tAVKH
0.7
---
0.8
---
1.0
---
ns
Address Input Hold Time
tKHAX
0.4
---
0.5
---
0.5
---
ns
Control Input Setup Time
tBVKH
0.7
---
0.8
---
1.0
---
ns
1
Control Input Hold Time
tKHBX
0.4
---
0.5
---
0.5
---
ns
1
Data Input Setup Time
tDVKH
tDVKL
0.35
---
0.4
---
0.45
---
ns
Data Input Hold Time
tKHDX
tKLDX
0.3
---
0.35
---
0.4
---
ns
Input Clock High to Output Data Valid
Input Clock Low to Output Data Valid
tKHQV
tKLQV
---
1.8
---
2.1
---
2.3
ns
Input Clock High to Output Data Hold
Input Clock Low to Output Data Hold
tKHQX
tKLQX
0.5
---
0.5
---
0.5
---
ns
2
Input Clock High to Output Data Low-Z
tKHQX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Data High-Z
tKHQZ
---
1.8
---
2.1
---
2.3
ns
2,3
Input Clock High to Output Clock High
Input Clock Low to Output Clock Low
tKHCH
tKLCL
0.5
1.8
0.5
2.1
0.5
2.3
ns
Input Clock High to Output Clock Low-Z
tKHCX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Clock High-Z
tKHCZ
---
1.8
---
2.1
---
2.3
ns
2,3
Output Clock High to Output Data Valid
Output Clock Low to Output Data Valid
tCHQV
tCLQV
---
0.25
---
0.25
---
0.3
ns
2
Output Clock High to Output Data Hold
Output Clock Low to Output Data Hold
tCHQX
tCLQX
-0.25
---
-0.25
---
-0.3
---
ns
2


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