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FT10001 Fiches technique(PDF) 9 Page - ON Semiconductor |
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FT10001 Fiches technique(HTML) 9 Page - ON Semiconductor |
9 / 13 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FT10001 • Rev 1.0.1 8 Physical Dimensions Figure 6. 6-Lead MicroPak2™ 1.0 x 1.0mm, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. 1.00 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD 0.05 C A B 0.55MAX 0.05 C C 0.35 0.09 0.19 12 3 0.35 0.25 5X 6X DETAIL A 0.60 (0.08) 4X (0.05) 6X 0.40 0.30 0.075X45° CHAMFER 5X 0.40 0.35 1X 0.45 6X 0.19 TOP VIEW BOTTOM VIEW 0.66 0.10 CB A .05 C PIN 1 0.05 C 2X 2X 1.00 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC E. DRAWING FILENAME AND REVISION: MGF06AREV3 0.52 0.73 0.57 0.20 6X 1X 5X RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB DETAIL A PIN 1 LEAD SCALE: 2X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION DESIGN. 0.90 MIN 250uM 6 54 0.35 (0.08) 4X SIDE VIEW |
Numéro de pièce similaire - FT10001 |
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Description similaire - FT10001 |
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