NBSG53ABAEVB datasheet(9/18 Pages) ONSEMI

No de pièce	NBSG53ABAEVB

Description	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS

Download	18 Pages

Scroll/Zoom	100%

Fabricant	ONSEMI [ON Semiconductor]

Site Internet	http://www.onsemi.com

Logo

9 / 18 page

NBSG53A

http://onsemi.com

9

Table 10. AC CHARACTERISTICS for FCBGA−16

VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V

−40

°C

25

°C

70

°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

fmax

Maximum Frequency

(See Figures 4, 6, 8, 10, and 11)

DFF

(See Figures 5, 7, 9, 10, and 11)

(Note 26)

DIV/2

8

10

8

10

8

10

GHz

tPLH,

tPHL

Propagation Delay to Output Differential

CLK

→Q, Q

(OLS = VCC)

(OLS = VCC − 0.4 V)

(OLS = VCC − 0.8 V, OLS = FLOAT)

**(OLS = VEE)

160

150

155

210

200

205

260

250

255

160

155

160

215

205

210

270

255

260

165

160

220

210

215

275

260

270

ps

SEL

→Q, Q

(OLS = VCC)

(OLS = VCC − 0.4 V)

(OLS = VCC − 0.8 V, OLS = FLOAT)

**(OLS = VEE)

165

160

220

210

215

210

275

260

270

260

170

160

165

160

225

210

220

215

280

260

275

270

170

160

165

225

210

220

280

260

275

R

→Q, Q

(OLS = VCC) DIV/2

(OLS = VCC) DFF

(OLS = VCC − 0.4 V) DIV/2

(OLS = VCC − 0.4 V) DFF

(OLS = VCC −0.8 V, OLS = FLOAT) DIV/2

(OLS = VCC − 0.8 V, OLS = FLOAT) DFF

**(OLS = VEE) DIV/2

**(OLS = VEE) DFF

220

200

215

195

220

200

215

195

295

270

285

260

290

265

285

260

370

340

355

325

360

330

355

325

225

205

220

200

220

200

220

200

300

275

290

265

295

270

290

265

375

345

360

330

370

340

360

330

225

205

220

200

220

200

220

200

300

275

290

265

295

270

290

265

375

345

360

330

370

340

360

330

tSKEW

Duty Cycle Skew (Notes 27 and 29)

DFF

5

20

5

20

5

20

ps

tJITTER

RMS Random Clock Jitter

fin v 8 GHz

(See Figures 4 and 6) (Note 26)

Peak−to−Peak Data Dependent Jitter

fin = 8 Gb/s

0.5

1.5

0.5

TBD

1.5

0.5

1.5

ps

VINPP

Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 28)

75

2600

75

2600

75

2600

mV

tr

tf

Output Rise/Fall Times (20% − 80%)

@ 1 GHz

Q, Q

(OLS = VCC)

(OLS = VCC − 0.4 V)

(OLS = VCC − 0.8 V, OLS = FLOAT)

**(OLS = VEE)

30

20

25

50

40

45

65

60

65

30

20

25

50

40

45

65

60

65

30

20

25

50

40

45

65

60

65

ps

ts

Setup Time

D

→CLK

30

14

30

10

30

13

ps

th

Hold Time

D

→CLK

25

12

25

7

25

9

ps

trr

Reset Recovery

DFF, DIV/2

40

9

40

12

40

10

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

26. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50

W to

VCC − 2.0 V. Input edge rates is 40 ps (20% − 80%).

27. See Figure 14. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.

28. VINPP (MAX) cannot exceed VCC − VEE (Applicable only when VCC − VEE < 2600 mV).

29. See Figure 10. Duty Cycle % vs. Frequency.

**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.

Numéro de pièce similaire - NBSG53ABAEVB

Fabricant	No de pièce	Fiches technique	Description
ON Semiconductor	NBSG53ABAEVB	152Kb / 18P	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip?묯lop/Clock Divider with Reset and OLS July, 2006 ??Rev. 8

More results

Description similaire - NBSG53ABAEVB

Fabricant	No de pièce	Fiches technique	Description
ON Semiconductor	NBSG53A	152Kb / 18P	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip?묯lop/Clock Divider with Reset and OLS July, 2006 ??Rev. 8
ON Semiconductor	NBSG53A	167Kb / 17P	2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider June, 2014 ??Rev. 15
Micrel Semiconductor	SY10EP53V	52Kb / 5P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET
	SY10EP53V	64Kb / 6P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET
	SY10EP53V	86Kb / 6P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET
	SY10EP51V	498Kb / 7P	5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK
	SY10EP51V	575Kb / 8P	5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK
ON Semiconductor	MC10EP51	76Kb / 8P	3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock April, 2001 ??Rev. 3
Micrel Semiconductor	SY10EP52V	117Kb / 7P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP
ON Semiconductor	MC100LVEL29	114Kb / 3P	Dual Differential Data and Clock D Flip-Flop With Set and Reset 1996 REV 1

More results

NBSG53ABAEVB Fiches technique(PDF) 9 Page - ON Semiconductor

NBSG53ABAEVB Fiches technique(HTML) 9 Page - ON Semiconductor

Numéro de pièce similaire - NBSG53ABAEVB

Description similaire - NBSG53ABAEVB

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Fiches technique Télécharger

Lien URL