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BTS50020-1TAD Fiches technique(PDF) 16 Page - Infineon Technologies AG |
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BTS50020-1TAD Fiches technique(HTML) 16 Page - Infineon Technologies AG |
16 / 51 page Data Sheet 16 Rev. 1.1 2017-03-28 BTS50020-1TAD Smart High-Side Power Switch Functional Description 5 Functional Description 5.1 Power Stage The power stage is built by a N-channel power MOSFET (DMOS) with charge pump. 5.1.1 Output ON-State Resistance The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ. Page 42 shows the dependencies in terms of temperature and supply voltage, for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 5.3.5. A HIGH signal (see Chapter 5.2) at the input pin causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission. 5.1.2 Switching Resistive Loads Figure 8 shows the typical timing when switching a resistive load. The power stage has a defined switching behavior. Defined slew rates results in lowest EMC emission at minimum switching losses. Figure 8 Switching a Resistive Load: Timing 5.1.3 Switching Inductive Loads 5.1.3.1 Output Clamping When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a Infineon® SMART CLAMPING mechanism implemented that keeps negative output voltage to a certain level (VS - VDS(CL)). Please refer to Figure 9 and Figure 10 for details. Nevertheless, the maximum allowed load inductance remains limited. VOUT 50% VS 25% VS 10% VS 90% VS VOUT IOUT IOUT VIN VIN tOFF(DELAY) tOFF tON(DELAY) tON dVON/dt dVOFF/dt |
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Description similaire - BTS50020-1TAD |
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