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AK5522 Fiches technique(PDF) 50 Page - Asahi Kasei Microsystems

No de pièce AK5522
Description  Differential Input Stereo 32-bit ADC with Excellent PSRR
Download  84 Pages
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Fabricant  AKM [Asahi Kasei Microsystems]
Site Internet  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK5522 Fiches technique(HTML) 50 Page - Asahi Kasei Microsystems

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[AK5522]
017002311-E-00
2017/03
- 50 -
External Master Mode (Parallel Control Mode)
Figure 45. Power-up Sequence (Parallel Control mode, EXT Master Mode)
(1) Input MCLK after power on the power supplies.
(2) Raise the PDN pin from
“L” to “H”. The PDN pin should be held to “L” for more than 150 ns after power
on the power supplies.
(3) The internal regulator for digital core powers up after 17.8ms (max.) from a rising edge of the PDN pin.
This timing is counted by the internal oscillator.
(4) The VREF pin outputs reference voltage after 35.7ms (max.@fs=48kHz) from the rising edge of the
PDN pin.
(5) The REGAO pin outputs 3.3V after 42.7ms (max.@fs=48kHz) from the rising edge of the PDN pin.
(6) The SDTO pin starts outputting A/D data after 102.9ms (max.@fs=48kHz) from the rising edge of the
PDN pin.
(7) The LRCK and BICK pins start outputting clocks after 17.8ms (max.) from the rising edge of the PDN
pin.
Wait time (4), (5) and (6) depend on the sampling frequency as shown in the expressions below.
(4): 27.8ms+378
n/fs (max.)
(5): 22.8ms+953
n/fs (max.)
(6): 17.8ms+4086
n/fs (max.)
Normal speed: n=1, Double speed: n=2, Quad speed: n=4
AVDD pin
DVDD pin
MCLK pin (I)
PDN pin (I)
(2)
(1)
REGDO pin (O)
(DVDD=3.3V)
(3)
Hi-Z
VREF pin (O)
(4)
Hi-Z (Pull-down)
Output
REGAO pin (O)
(AVDD=5V)
(5)
Output
SDTO pin (O)
(6)
Output
(7)
LRCK pin (O)
BICK pin (O)
REGDO pin (I)
(DVDD=1.8V)
REGAO pin (O)
(AVDD=3.3V)
Hi-Z (Pull-down)
Hi-Z (Pull-down)


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