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74GTLP2033DGGRE4 Fiches technique(PDF) 10 Page - Texas Instruments |
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74GTLP2033DGGRE4 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 15 page SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN MAX UNIT fclock Clock frequency 175 MHz tw Pulse duration CLKAB/LEAB or CLKBA/LEBA 2.8 ns AI before CLKAB ↑ 1.1 AI before CLKBA ↑ 1.4 t Setup time B before CLKBA ↑ 1 ns tsu Setup time AI before LEAB ↓ 1.6 ns AI before LEBA ↓ 2.1 B before LEBA ↓ 2.2 AI after CLKAB ↑ 0.3 AI after CLKBA ↑ 0.2 th Hold time B after CLKBA ↑ 0.6 ns th Hold time AI after LEAB ↓ 0.3 ns AI after LEBA ↓ 0 B after LEBA ↓ 0 |
Numéro de pièce similaire - 74GTLP2033DGGRE4 |
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Description similaire - 74GTLP2033DGGRE4 |
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