TSL1406R, TSL1406RS

768 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS042 – AUGUST 2002

2

t

t

Copyright

E 2002, TAOS Inc.

The

LUMENOLOGY

r Company

www.taosinc.com

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AO1

6

O

Analog output, section 1.

AO2

12

O

Analog output, section 2.

CLK1

4

I

Clock, section 1. CLK1 controls charge transfer, pixel output, and reset.

CLK2

10

I

Clock, section 2. CLK2 controls charge transfer, pixel output, and reset.

GND

5

Ground (substrate). All voltages are referenced to GND.

HOLD1

3

I

Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in

serial mode, SI1 in parallel mode.

HOLD2

9

I

Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode.

SI1

2

I

Serial input (section 1). SI1 defines the start of the data-out sequence.

SI2

8

I

Serial input (section 2). SI2 defines the start of the data-out sequence.

SO1

7

O

Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode.

SO2

11

O

Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an

end-of-data indication.

13

Supply voltage for both analog and digital circuitry.

1

Normally grounded.

Detailed Description

The sensor consists of 768 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a

pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.

During the integration period, a sampling capacitor connects to the output of the integrator through an analog

switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel

and the integration time.

The output and reset of the integrators are controlled by a 384-bit shift register and reset logic. An output cycle

is initiated by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1

when SI1 and HOLD1 are connected together. This causes all 384 sampling capacitors to be disconnected from

their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift

register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output

amplifier that generates a voltage on analog output AO. The integrator reset period ends 18 clock cycles after

the SI pulse is clocked in. Then the next integration period begins. On the 384th clock rising edge, the SI pulse

is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (when SO1 is connected to

SI2). The rising edge of the 385th clock cycle terminates the SO1 pulse, and returns the analog output AO of

section 1 to high-impedance state. Similarly, SO2 is clocked out on the 768th clock pulse. Note that a 769th clock

pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. Sections

1 and 2 may be operated in parallel or in serial fashion.