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S29GL512N Fiches technique(PDF) 7 Page - Cypress Semiconductor |
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S29GL512N Fiches technique(HTML) 7 Page - Cypress Semiconductor |
7 / 92 page Document Number: 002-01522 Rev. *B Page 7 of 92 S29GL512N S29GL256N S29GL128N 3.1 Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. 4. Pin Description 5. Logic Symbol Figure 5.1 S29GL512N A24–A0 25 Address inputs (512 Mb) A23–A0 24 Address inputs (256 Mb) A22–A0 23 Address inputs (128 Mb) DQ14–DQ0 15 Data inputs/outputs DQ15/A-1 DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# Chip Enable input OE# Output Enable input WE# Write Enable input WP#/ACC Hardware Write Protect input; Acceleration input RESET# Hardware Reset Pin input BYTE# Selects 8-bit or 16-bit mode RY/BY# Ready/Busy output VCC 3.0 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage supply tolerances) VIO Output Buffer power VSS Device Ground NC Pin Not Connected Internally 25 16 or 8 DQ15–DQ0 (A-1) A24–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO BYTE# |
Numéro de pièce similaire - S29GL512N |
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Description similaire - S29GL512N |
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