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ACT2861QI Fiches technique(PDF) 63 Page - Active-Semi, Inc |
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ACT2861QI Fiches technique(HTML) 63 Page - Active-Semi, Inc |
63 / 91 page ACT2861QI Rev 2.0, 27-Apr-2018 Innovative PowerTM www.active-semi.com ActiveSwitcherTM is a trademark of Active-Semi Copyright © 2018 Active-Semi, Inc. 63 REG 0x01: Main Control 2 (R/W) (NVM) Bit Name Description Comment 7 DIS_TH NVM 0: Enable 1: Disable Set 1 to disable TH output and the JEITA Control. During this mode, charger and OTG mode will always operate at full current and voltage settings. Note: This must be set to 1 to achieve the lowest possible input current. 6 DIS_OCP_SHUTDO WN NVM 0: Enable 1: Disable If set to 0, the device will be disabled if FET cycle by cycle current limit is detected for 8 (or 16) continuous cycles. For both Charge and OTG modes. Uses the FET_LIMIT register setting for the FET ILIM. 5 DIS_VBAT_OVP NVM 0: Enable 1: Disable When set to 1, a BAT_OVP fault does not latch off the charger in a fault mode. Charger will restart automatically when the OVP condition is removed. 4 FET_ILimit NVM 0: 8.5A 1: 10A This is the cycle by cycle current limit setting for ALL FETS in any operating mode: 3 VIN_OV_RESTART_ DELAY NVM 0: 40ms 1: 100usec Delay time to restart in charger mode after Input OV fault has been removed 2 VREG_EN NVM 0: Turn OFF VREG 1: Turn ON VREG Control VREG on/off Default is on. 1 WATCHDOG[1] NVM 00: Disable timer 01: 80s 10: 160s 11: 320s I2C Watchdog Timer Setting Watchdog timer is always disabled and reset to 0 in HIZ Mode. When Disabled, Watchdog timer is also reset to 0. 0 WATCHDOG[0] NVM |
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