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MP2148 Fiches technique(PDF) 14 Page - Monolithic Power Systems

No de pièce MP2148
Description  1A Synchronous Step-down Converter with 11uA Iq in Ultra-small 1x1.5mm QFN
Download  20 Pages
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Fabricant  MPS [Monolithic Power Systems]
Site Internet  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP2148 Fiches technique(HTML) 14 Page - Monolithic Power Systems

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MP2148 –1A SYNCHRONOUS STEP-DOWN CONVERTER WITH 11µA IQ IN ULTRA-SMALL 1X1.5mm QFN
MP2148 Rev. 1.11
www.MonolithicPower.com
14
5/25/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
OPERATION
The MP2148 uses constant on-time control with
input voltage feed forward to stabilize the
switching frequency over the full input range. It
achieves 1A continuous output current from a
2.3V-to-5.5V input voltage with excellent load
and line regulation. The output voltage can be
regulated to as low as 0.6V.
Constant On-Time Control
Compare to fixed frequency PWM control,
constant on-time control offers a simpler control
loop and a faster transient response. By using
input-voltage
feed
forward,
the
MP2148
maintains a nearly constant switching frequency
across the input and output voltage ranges. The
switching pulse on time can be estimated as:
OUT
ON
IN
V
T
0.454 s
V
=⋅
μ
To prevent inductor current runaway during
load transient, MP2148 has fixed minimum off
time of 60ns.
Sleep Mode Operation
MP2148 features sleep mode to get high
efficiency at extreme light load. In sleep-mode,
most of the circuit blocks are turned off, except
the error amplifier and PWM comparator, thus
the operation current is reduced to a minimal
value, as Figure 2.
Figure 2: Operation Blocks at Sleep Mode
When the loading gets lighter, the ripple of the
output voltage is bigger and it drives the error
amplifier output (EAO) lower. When EAO hits
an internal low threshold, it will be clamped at
that level, MP2148 enters sleep mode. During
sleep mode, the valley of the FB pin voltage is
regulated to the internal reference voltage, thus,
the average output voltage is slightly higher
than the output voltage at DCM or CCM mode.
The on-time pulse at sleep mode is around 40%
larger than that on DCM or CCM mode. Figure
3
shows
the
average
FB
pin
voltage
relationship with the internal reference at sleep
mode.
Figure 3: FB Average Voltage at Sleep Mode
When MP2148 is in sleep mode, the average
output voltage is higher than the internal
reference voltage. The EAO is kept low and
clamped in sleep mode. When the loading
increases,
the
PWM
switching
period
decreases in order to keep the output voltage
regulated and the output voltage ripple is
decrease relatively. Once EAO is more than
internal low threshold, MP2148 will be out of
sleep mode and enter DCM or CCM mode
depending on the loading. In DCM or CCM
mode, the EA regulates the average output
voltage to the internal reference which is shown
in Figure 4.
Figure 4: DCM Mode Control
There is always a loading hysteresis of entering
sleep mode and leaving sleep mode due to the
error amplifier clamping response time.
AAM Operation at Light-Load Operation
The
MP2148
has
AAM
(Advanced
Asynchronous Modulation) power-save mode
together with ZCD (Zero Current Cross
Detection) circuit for light load.
The MP2148 has AAM power-save mode for
light load. Simplified AAM control theory is as
Figure 5. AAM current IAAM is set internally. The
SW on pulse time is decided by on-timer
generator and AAM comparator. At light load
condition, the SW on pulse time is the longer
one. If the AAM comparator pulse is longer than


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