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MP1475S Fiches technique(PDF) 12 Page - Monolithic Power Systems |
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MP1475S Fiches technique(HTML) 12 Page - Monolithic Power Systems |
12 / 19 page MP1475S – HIGH-EFFICIENCY, 3A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER MP1475S Rev. 1.0 www.MonolithicPower.com 12 1/8/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. current. The optimized, internal compensation network minimizes the external component count and simplifies the control loop design. Enable/SYNC Control EN/SYNC is a digital control pin that turns the regulator on and off. Drive EN/SYNC high to turn on the regulator; drive EN/SYNC low to turn off the regulator. An internal 1MΩ resistor from EN/SYNC to GND allows EN/SYNC to be floated to shut down the chip. EN/SYNC is clamped internally using a 6.5V series-Zener-diode (see Figure 4). Connecting EN/SYNC through a pull-up resistor to the voltage on IN limits the EN/SYNC input current to less than 100µA. For example, with 12V connected to IN, RPULLUP ≥ (12V – 6.5V) ÷ 100µA = 55kΩ. Connecting EN/SYNC directly to a voltage source without a pull-up resistor requires limiting the amplitude of the voltage source to ≤6V to prevent damage to the Zener diode. Figure 4. 6.5V Zener Diode Connection For external clock synchronization, connect a clock with a frequency range between 300kHz and 2MHz. The internal clock rising edge synchronizes with the external clock rising edge. Select an external clock signal with a pulse width less than 1.7μs. Under-Voltage Lockout (UVLO) The MP1475S has under-voltage lockout protection (UVLO). When the VCC voltage exceeds the UVLO rising threshold voltage, the device begins to power-up. The device shuts off when the VCC voltage drops below the UVLO falling threshold voltage. This is non-latch protection. The MP1475S is disabled when the input voltage falls below 3.2V. If an application requires a higher under-voltage lockout (UVLO) threshold, use EN/SYNC to adjust the input voltage UVLO using two external resistors (see Figure 5). For best results, set the UVLO falling threshold (VSTOP) above 4.5V using the enable resistors. Set the rising threshold (VSTART) to provide enough hysteresis to allow for input-supply variations. REN_UP REN_DOWN EN/SYNC Figure 5 . Adjustable UVLO Internal Soft-Start (SS) The soft-start prevents the converter output voltage from overshooting during start-up. When the chip starts up, the internal circuitry generates a soft-start voltage (VSS) that ramps up from 0V to 1.2V. When VSS is less than VREF, the error amplifier uses VSS as the reference. When VSS exceeds VREF, the error amplifier uses VREF as the reference. The SS time is set internally to 1.2ms. Pre-Bias Start-Up The MP1475S is designed for a monotonic start-up into pre-biased loads. If the output is pre-biased to a certain voltage during start-up, the BST voltage is refreshed and charged. Also, the voltage on the soft-start capacitor is charged. If BST voltage exceeds its rising threshold voltage, and the soft-start capacitor voltage exceeds the sensed-output voltage at FB, the device starts to operate normally. Power Good Indicator (PG) MP1475S has an open-drain pin as the power good indicator (PG). Pull PG up to VCC (or another external source) through a 100kΩ resistor. When VFB exceeds 90% of VREF, PG goes high (after a 0.6ms delay time). If VFB falls below 85% of VREF, an internal MOSFET pulls PG down to ground. |
Numéro de pièce similaire - MP1475S |
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Description similaire - MP1475S |
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