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OV6630 Fiches technique(PDF) 19 Page - List of Unclassifed Manufacturers |
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OV6630 Fiches technique(HTML) 19 Page - List of Unclassifed Manufacturers |
19 / 29 page SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS March 4, 2000 Version 1.0 19 3 I 2C Bus Many of the functions and configuration registers in the OV6630/OV6130 image sensors are available through the I 2C interface. The I 2C port is enabled by asserting the I2CB line (pin 12) through a 10K Ω resistor to V DD. When the I 2C capability is enabled (I2CB = 1), the OV6630/OV6130 imager operates as a slave device that supports up to 400 KBps serial transfer rate using a 7-bit address/data transfer protocol. – SLAVE TRANSMIT – MASTER TRANSMIT – MASTER INITIATE MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE) MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE) S SLAVE ID (7BITS) RW A SUB-ADDRESS (8BITS) A P START MSB LSB=0 ACK STOP 1ST BYTE 2ND BYTE S SLAVE ID (7BITS) RW A SUB-ADDRESS (8BITS) A DATA (8BITS) A P START MSB LSB=0 ACK ACK STOP 1ST BYTE 2ND BYTE 3RD BYTE MASTER RECEIVE, SLAVE TRANSMIT (READ CYCLE) S SLAVE ID (7BITS) RW A DATA (8BITS) A DATA (8BITS) 1 P START MSB LSB=1 ACK NO ACK IN LAST BYTE STOP 1ST BYTE 2ND BYTE 3RD BYTE SLAVE ID - 110CCC0X S - START CONDITION A - ACKNOWLEDGE BIT P - STOP CONDITION CS2 (PIN 35) CS1 (PIN 37) CS0 (PIN 34) X - RW BIT, 1:READ, 0:WRITE Figure 8. I 2C Bus Protocol Format 3.1 I2C Bus Protocol Format In I 2C operation, the master must perform the following operations: - Generate the start/stop condition - Provide the serial clock on SCL - Place the 7-bit slave address, the RW bit, and the 8-bit sub- address on SDA The receiver must pull down SDA during the acknowledge period. During the write cycle, OV6630/OV6130 returns acknowledge and, |
Numéro de pièce similaire - OV6630 |
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Description similaire - OV6630 |
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