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ADS5272 Datasheet(Fiches technique) 4 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Numéro de pièce ADS5272
Description  8-Channel, 12-Bit, 65MSPS ADC with Serial LVDS Interface
Télécharger  16 Pages
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Fabricant  BURR-BROWN [Burr-Brown (TI)]
Site Internet  http://www.burr-brown.com
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 4 page
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ADS5272
SBAS324 − JUNE 2004
www.ti.com
4
AC CHARACTERISTICS
TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,
−1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
87
dBc
SFDR
Spurious-Free Dynamic Range
fIN = 5MHz
TBD
85
dBc
SFDR
Spurious-Free Dynamic Range
fIN = 10MHz
85
dBc
fIN = 20MHz
83
dBc
fIN = 1MHz
90
dBc
HD2 2nd-Order Harmonic Distortion
fIN = 5MHz
TBD
90
dBc
HD2 2nd-Order Harmonic Distortion
fIN = 10MHz
89
dBc
fIN = 20MHz
86
dBc
fIN = 1MHz
87
dBc
HD3 3rd-Order Harmonic Distortion
fIN = 5MHz
TBD
85
dBc
HD3 3rd-Order Harmonic Distortion
fIN = 10MHz
85
dBc
fIN = 20MHz
83
dBc
fIN = 1MHz
70.5
dBFS
SNR
Signal-to-Noise Ratio
fIN = 5MHz
TBD
70.5
dBFS
SNR
Signal-to-Noise Ratio
fIN = 10MHz
70.5
dBFS
fIN = 20MHz
70.5
dBFS
fIN = 1MHz
70
dBFS
SINAD
Signal-to-Noise and Distortion
fIN = 5MHz
TBD
70
dBFS
SINAD
Signal-to-Noise and Distortion
fIN = 10MHz
70
dBFS
fIN = 20MHz
70
dBFS
IMD
Two-Tone Intermodulation Distortion
f1 = 9.5MHz at −7dBFS
−85
dBFS
IMD
Two-Tone Intermodulation Distortion
f2 = 10.2MHz at −7dBFS
−85
dBFS
ENOB
Effective Number of Bits
fIN = 5MHz
11.3
Bits
Crosstalk
Signal Applied to 7 Channels;
Measurement Taken on the Channel with
No Input Signal
−90
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance
between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between the differential LVDS pins and ground. CLOAD includes the
receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100
Ω differential impedance between the device and
the load. All LVDS specifications are functionally tested, but not parametrically tested.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS(1)
VOH Output Voltage High, OUTP or OUTN
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 7
1375
1500
mV
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω ± 1%
900
1025
mV
 VOD Output Differential Voltage,  OUTP − OUTN
RLOAD = 100Ω ± 1%
300
350
400
mV
VOS Output Offset Voltage(2)
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 7
1100
1200
1300
mV
CO
Output Capacitance(3)
VCM = 1.5V
4
pF
 ∆VOD Change in  VOD Between 0 and 1
RLOAD = 100Ω ± 1%
25
mV
∆VOS Change Between 0 and 1
RLOAD = 100Ω ± 1%
25
mV
ISOUT
Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
ISOUTNP Output Current
Drivers Shorted Together
12
mA
DRIVER AC SPECIFICATIONS
Clock
Clock Signal Duty Cycle
6
× ADCLK
45
50
55
%
Minimum Data Setup TIme(4, 5)
650
ps
Minimum Data Hold Time(4, 5)
650
ps
tRISE/tFALL VOD Rise Time or VOD Fall Time
IO = 2.5mA
400
IO = 3.5mA
250
ps
IO = 4.5mA
200
ps
IO = 6mA
150
ps
(1) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2) VOS refers to the common-mode of OUTP and OUTN.
(3) Output capacitance inside the device, from either OUTP or OUTN to ground.
(4) Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock
paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.




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