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CSP2510D Fiches technique(PDF) 1 Page - Integrated Device Technology |
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CSP2510D Fiches technique(HTML) 1 Page - Integrated Device Technology |
1 / 9 page 1 0 °CTO85°CTEMPERATURERANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER OCTOBER 2001 2001 Integrated Device Technology, Inc. DSC-5874/2 c IDTCSP2510D 0ºººººC TO 85ºººººC TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER DESCRIPTION: The CSP2510D is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. ItisspecificallydesignedforusewithsynchronousDRAMs.TheCSP2510D operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Outputsignaldutycyclesareadjustedto50percent,independentoftheduty cycleatCLK.TheoutputscanbeenabledordisabledviathecontrolGinput. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510D does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CSP2510D requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground. TheCSP2510Disspecifiedforoperationfrom0°Cto+85°C. Thisdevice is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details. 21 Y9 PLL 3 5 8 9 4 Y0 Y1 Y2 Y3 Y4 15 17 20 16 Y5 Y6 Y7 Y8 24 13 23 AV DD FB IN CLK G 11 12 FBOUT FUNCTIONAL BLOCK DIAGRAM The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.3V VDD • tpd Phase Error at 166MHz: < ±150ps • Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz • Spread Spectrum Compatible • Operating frequency 50MHz to 175MHz • Available in 24-Pin TSSOP package APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations |
Numéro de pièce similaire - CSP2510D |
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Description similaire - CSP2510D |
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