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AD5247BKS5-R2 Fiches technique(PDF) 3 Page - Analog Devices |
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AD5247BKS5-R2 Fiches technique(HTML) 3 Page - Analog Devices |
3 / 20 page AD5247 ELECTRICAL CHARACTERISTICS—5 kΩ VERSION Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect –1.5 ±0.1 +1.5 LSB Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect –4 ±0.75 +4 LSB Nominal Resistor Tolerance3 ∆RAB –30 +30 % Resistance Temperature Coefficient ∆RAB/∆T VA = VDD, Wiper = No Connect 45 ppm/°C RWB RWB Code = 0x00 75 300 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB Integral Nonlinearity4 INL –1 ±0.2 +1 LSB Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x40 15 ppm/°C Full-Scale Error VWFSE Code = 0x7F –3 –2 0 LSB Zero-Scale Error VWZSE Code = 0x00 0 +1 +2 LSB RESISTOR TERMINALS Voltage Range5 VB, W GND VDD V Capacitance6 A CA f = 1 MHz, Measured to GND, Code = 0x40 45 pF Capacitance6 W CW f = 1 MHz, Measured to GND, Code = 0x40 60 pF Common-Mode Leakage ICM VA = VDD/2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V 2.4 V Input Logic Low VIL VDD = 5 V 0.8 V Input Logic High VIH VDD = 3 V 2.1 V Input Logic Low VIL VDD = 3 V 0.6 V Input Current IIL VIN = 0 V or 5 V ±1 µA Input Capacitance6 CIL 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2.7 5.5 V Supply Current IDD VIH = 5 V or VIL = 0 V 3 8 µA Power Dissipation7 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 40 µW Power Supply Sensitivity PSSR VDD = +5 V ± 10%, Code = Midscale ±0.003 ±0.05 %/% DYNAMIC CHARACTERISTICS6, 8 Bandwidth –3 dB BW_5K RAB = 5 kΩ, Code = 0x40 1.2 MHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 % VW Settling Time tS VA = 5 V, ±1 LSB Error Band 1 µs Resistor Noise Voltage Density eN_WB RWB = 2.5 kΩ, RS = 0 Ω 6 nV/√Hz 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. Rev. 0 | Page 3 of 20 |
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