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CY7C1521KV18 Fiches technique(PDF) 8 Page - Cypress Semiconductor |
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CY7C1521KV18 Fiches technique(HTML) 8 Page - Cypress Semiconductor |
8 / 29 page Document Number: 001-00439 Rev. *M Page 8 of 29 CY7C1521KV18 current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5 × the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 , with VDDQ =1.5 V. The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR II to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the DDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 22. PLL These chips use a Phase Locked Loop (PLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock it to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). Application Example Figure 2 shows two DDR II used in an application. Figure 2. Application Example (Width Expansion) DQ[x:0] ALD R/W BWS KK ZQ SRAM#1 CQ/CQ DQ[x:0] ALD BWS KK ZQ SRAM#2 CQ/CQ DQ[2x:0] ADDRESS BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K FPGA / ASIC RQ RQ R/W LD R/W CC CC DELAYED K DELAYED K |
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