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CY7C1461KV33 Fiches technique(PDF) 7 Page - Cypress Semiconductor

No de pièce CY7C1461KV33
Description  36-Mbit (1M36/2M18) Flow-Through SRAM with NoBL??Architecture
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1461KV33 Fiches technique(HTML) 7 Page - Cypress Semiconductor

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CY7C1461KV33
CY7C1463KV33
Document Number: 001-66681 Rev. *G
Page 7 of 23
Pin Definitions
Pin Name
I/O
Description
A0, A1, A
Input-Synchronous Address Inputs. Used to select one of the address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB,
BWC, BWD
Input-Synchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
WE
Input-Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-Synchronous Advance or Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After deselecting, drive ADV/LD LOW
to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select or deselect the device.
CE2
Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select or deselect the device.
CE3
Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select or deselect the device.
OE
Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected.
CEN
Input-Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ
Input-Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/O-Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D]
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
I/O-Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power Supply
Power Supply Inputs to the Core of the Device.
VDDQ
I/O Power Supply Power Supply for I/O Circuitry.
VSS
Ground
Ground for the Device.
NC
N/A
No Connects. Not internally connected to the die.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.


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