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CY2VC521-2 Fiches technique(PDF) 4 Page - Cypress Semiconductor

No de pièce CY2VC521-2
Description  Low Noise LVDS Clock Generator with VCXO
Download  9 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2VC521-2 Fiches technique(HTML) 4 Page - Cypress Semiconductor

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CY2VC521-2
Document Number: 001-15599 Rev. *E
Page 4 of 9
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN
[1]
Input Voltage, DC
Relative to VSS
–0.5
VDD+0.5
V
TS
Temperature, Storage
Non Operating
–65
150
°C
TJ
Temperature, Junction
135
°C
ESDHBM
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
2000
V
UL–94
Flammability Rating
At 1/8 in.
V–0
Θ
JA
[5]
Thermal Resistance, Junction to Ambient
0 m/s airflow
84
°C/W
1 m/s airflow
79
2.5 m/s airflow
76
Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
VDD
Supply Voltage Range
3.15
3.3
3.45
V
TPU
Power up time for VDD to reach VDD(min). (Ensure power ramp is monotonic.)
0.05
500
ms
TA
Ambient Temperature
0
70
°C
Crystal Characteristics
Parameter
Description
Min
Typ
Max
Unit
Mode of Oscillation
Fundamental
F
Frequency
–27–
MHz
CL
Load Capacitance
14
pF
ESR
Equivalent Series Resistance
50
Ω
CS
Shunt Capacitance
7
pF
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
IDD
[3]
Power Supply Current
Outputs on and terminated
120
mA
VOD
LVDS Differential Output Voltage
247
350
454
mV
ΔV
OD
LVDS VOD Magnitude Change
–50
50
mV
VOS
LVDS Offset Output Voltage
1.125
1.25
1.375
mV
ΔV
OS
LVDS VOS Magnitude Change
–25
25
mV
VIH
Input High Voltage, SEL
0.7*VDD
––
V
VIL
Input Low Voltage, SEL
0.3*VDD
V
IIH
Input High Current, SEL
SEL = VDD
––
10
μA
IIL
Input Low Current, SEL
SEL = VSS
––
20
μA
CIN
[5]
Input Capacitance, SEL
4
pF
VVIN
VIN Input Voltage
0
VDD
V
IVIN
VIN Input Current
VSS ≤ VIN ≤ VDD
–10
60
μA
INLVIN
[4, 5]
VIN to FOUT Integral Nonlinearity
VSS ≤ VIN ≤ VDD
–1–
%
Notes
1. The voltage on any input or output pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper
(2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model
3. IDD includes ~8 mA of current that is dissipated externally in the output termination resistors.
4. Not 100% tested, guaranteed by design and characterization.
5. Integral nonlinearity is defined in IEEE Standard 1241-2000.
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