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ADS5240 Datasheet(Fiches technique) 6 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Numéro de pièce ADS5240
Description  4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
Télécharger  24 Pages
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Fabricant  BURR-BROWN [Burr-Brown (TI)]
Site Internet  http://www.burr-brown.com
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 6 page
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LVDS DIGITAL DATA AND CLOCK OUTPUTS
SWITCHING CHARACTERISTICS
ADS5240
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
Test conditions at I
O = 3.5mA, RLOAD = 100Ω, and CLOAD = 6pF. IO refers to the current setting for the LVDS buffer. RLOAD is
the differential load resistance between the LVDS pair. C
LOAD is the effective single-ended load capacitance between each of
the LVDS pins and ground. C
LOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are
done with a transmission line of 100
Ω characteristic impedance between the device and the load. All LVDS specifications are
characterized, but not tested at production.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS (1)
Output Voltage High, OUTP or OUTN
RLOAD = 100Ω± 1%
1375
1500
mV
VOH
See LVDS Timing Diagram, Page 7
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω± 1%
900
1025
mV
|VOD| Output Differential Voltage, |OUTP - OUTN|
RLOAD = 100Ω± 1%
300
350
400
mV
VOS Output Offset Voltage(2)
RLOAD = 100Ω± 1%
1100
1200
1300
mV
See LVDS Timing Diagram, Page 7
CO Output Capacitance(3)
VCM = 1.5V
4
pF
|
∆V
OD|
Change in |VOD| Between 0 and 1
RLOAD = 100Ω± 1%
25
mV
∆V
OS
Change Between 0 and 1
RLOAD = 100Ω± 1%
25
mV
ISOUT Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
ISOUTNP Output Current
Drivers Shorted Together
12
mA
DRIVER AC SPECIFICATIONS
Clock LVDS Clock Duty Cycle
6
× ADCLK (LCLK
P, LCLKN)
45
50
55
%
Minimum Data Setup Time(4)(5)
650
ps
Minimum Data Hold Time(4)(5)
650
ps
tRISE/tFALL VOD Rise Time or VOD Fall Time
IO = 2.5mA
400
ps
IO = 3.5mA
250
ps
IO = 4.5mA
200
ps
IO = 6mA
150
ps
(1)
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2)
VOS refers to the common-mode of OUTP and OUTN.
(3)
Output capacitance inside the device, from either OUTP or OUTN to ground.
(4)
Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margins.
T
MIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, -1dBFS, I
SET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted.
ADS5240
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING SPECIFICATIONS
tSAMPLE
25
50
ns
tD(A) Aperture Delay
3.1
ns
Aperture Jitter (uncertainty)
1
ps rms
tD(pipeline) Latency
6.5
Cycles
tPROP Propagation Delay
5
ns
6




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