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ADS5240 Datasheet(Fiches technique) 19 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Numéro de pièce ADS5240
Description  4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
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Fabricant  BURR-BROWN [Burr-Brown (TI)]
Site Internet  http://www.burr-brown.com
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LVDS BUFFERS
NOISE COUPLING ISSUES
External
Termination
Resistor
OUT
P
High
Low
OUT
N
Low
High
ADS5240
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
of the clock tree for matching introduces an aperture
The LVDS buffer gets data from a serializer that
delay, which is defined as the delay between the
takes the output data from each channel and
rising edge of ADCLK and the actual instant of
serializes it into a single data stream. For a clock
sampling. The aperture delays for all the channels
frequency of 40MHz, the data rate output by the
are matched. The aperture delays for all channels are
serializer is 480MBPS. The data comes out LSB first,
matched. However, across conditions of temperature,
with a register programmability to revert to MSB first.
supply voltage, and devices, the aperture delay
The serializer also gives out a 1x clock and a 6x
averages 3.1ns.
clock. The 6x clock (denoted as LCLKP/LCLKN) is
meant to synchronize the capture of the LVDS data.
The input ADCLK should ideally have a 50% duty
The deskew mode can be enabled as well, using a
cycle. However, while routing ADCLK to different
register setting. This mode gives out a data stream of
components on board, the duty cycle of the ADCLK
alternate 0s and 1s and can be used determine the
reaching the ADS5240 could deviate from 50%. A
relative delay between the 6x clock and the output
smaller (or larger) duty cycle eats into the time
data for optimum capture. A 1x clock is also gener-
available for sample or hold phases of each circuit,
ated by the serializer and transmitted by the LVDS
and is therefore not optimal. For this reason, the
buffer. The 1x clock (referred to as ADCLKP/ADCLKN)
internal PLL is used to generate an internal clock that
is used to determine the start of the 12-bit data
has 50% duty cycle.
frame. The sync mode (enabled through a register
setting) gives out a data of six 0s followed by six 1s.
The use of the PLL automatically dictates the mini-
Using this mode, the 1x clock can be used to
mum sampling rate to be about 20MSPS.
determine the start of the data frame. In addition to
the deskew mode pattern and the sync pattern, a
custom pattern can be defined by the user and output
The LVDS buffer has two current sources, as shown
from the LVDS buffer.
in Figure 17. OUTP and OUTN are loaded externally
by a resistive load that is ideally about 100
Ω.
Depending on the data being 0 or 1, the currents are
High-speed mixed signals are sensitive to various
directed in one or the other direction through the
types of noise coupling. One of the main sources of
resistor. While the lower side current source is a
noise is the switching noise from the serializer and
constant current source, the higher side current
the output buffers. Maximum care is taken to isolate
source is controlled through a feedback loop to
these noise sources from the sensitive analog blocks.
maintain the output common mode constant. The
As a starting point, the analog and digital domains of
LVDS buffer has four current settings. The default
the chip are clearly demarcated. AVDD and AVSS
current setting is 3.5mA, and gives a differential drop
are used to denote the supplies for the analog
of about
±350mV across the 100Ω resistor.
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the
device.
The
extent
of
noise
coupled
and
transmitted from the digital to the analog sections
depends on the following:
1. The
effective
inductances
of
each
of
the
supply/ground sets.
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground
pins leads to better suppression of the noise. For this
reason,
multiple
pins
are
used
to
drive
each
supply/ground. It is also critical to ensure that the
impedances of the supply and ground lines on board
are kept to the minimum possible values. Use of
ground planes in the board as well as large decoup-
ling capacitors between the supply and ground lines
are necessary to get the best possible SNR from the
device.
Figure 17. LVDS Buffer
19




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