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ADS5240 Datasheet(Fiches technique) 17 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Numéro de pièce ADS5240
Description  4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
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Fabricant  BURR-BROWN [Burr-Brown (TI)]
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 17 page
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CM Buffer
The ADS5240 is a 4-channel, high-speed, CMOS
The analog input biasing is shown in Figure 14. The
recommended method to drive the inputs is through
sample-and-hold circuit at the input, followed by a
AC coupling. AC coupling removes the worry of
12-bit ADC. The 12 bits given out by each channel
setting the common-mode of the driving circuit, since
are serialized and sent out on a single pair of pins in
the inputs are biased internally using two 600
LVDS format. All four channels of the ADS5240
operate from a single clock referred to as ADCLK.
The sampling clocks for each of the four channels are
generated from the input clock using a carefully
matched clock buffer tree. The 12x clock required for
the serializer is generated internally from ADCLK
using a phase lock loop (PLL). A 6x and a 1x clock
are also output in LVDS format along with the data to
enable easy data capture. The ADS5240 operates
from internally-generated reference voltages that are
trimmed to improve matching across multiple devices
on a board. This feature eliminates the need for
external routing of reference lines and also improves
matching of the gain across devices. The nominal
values of REFT and REFB are 2V and 1V, respect-
ively. These values imply that a differential input of
-1V corresponds to the zero code of the ADC, and a
differential input of +1V corresponds to the full-scale
Figure 14. Analog Input Bias Circuitry
code (4095 LSB). VCM (common-mode voltage of
REFT and REFB) is also made available externally
through a pin, and is nominally 1.5V.
The sampling capacitor used to sample the inputs is
4pF. The choice of the external AC coupling capacitor
The ADC employs a pipelined converter architecture
is dictated by the attenuation at the lowest desired
consisting of a combination of multi-bit and single-bit
input frequency of operation. The attenuation re-
internal stages. Each stage feeds its data into the
sulting from using a 10nF AC coupling capacitor is
digital error correction logic, ensuring excellent differ-
ential linearity and no missing codes at the 12-bit
level. The pipeline architecture results in a data
If the input is DC-coupled, then the output com-
latency of 6.5 clock cycles.
mon-mode voltage of the circuit driving the ADS5240
should match the VCM (which is provided as an output
The output of the ADC goes to a serializer that
pin) to within
±50mV. It is recommended that the
operates from a 12x clock generated by the PLL. The
output common-mode of the driving circuit be derived
12 data bits from each channel are serialized and
from VCM provided by the device.
sent LSB first. In addition to serializing the data, the
serializer also generates a 1x clock and a 6x clock.
The sampling circuit consists of a low-pass RC filter
These clocks are generated in the same way the
at the input to filter out noise components that might
serialized data is generated, so these clocks maintain
be differentially coupled on the input pins. The inputs
perfect synchronization with the data. The data and
are sampled on two 4pF capacitors, see Figure 15.
clock outputs of the serializer are buffered externally
The sampling on the capacitors is done with respect
using LVDS buffers. Using LVDS buffers to transmit
to an internally-generated common-mode voltage
data externally has multiple advantages, such as
(INCM). The switches connecting the sampling ca-
reduced number of output pins (saving routing space
pacitors to the INCM are opened out first (before the
on the board), reduced power consumption, and
switches connecting them to the analog inputs). This
reduced effects of digital noise coupling to the analog
ensures that the charge injection arising out of the
circuit inside the ADS5240.
switches opening is independent of the input signal
amplitude to a first-order of approximation. SP refers
The ADS5240 operates from two sets of supplies and
to a sampling clock whose falling edge comes an
grounds. The analog supply/ground set is denoted as
instant before the SAMPLE clock. The falling edge of
AVDD/AVSS, while the digital set is denoted by
SP determines the sampling instant.

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