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AD8383ACPZ Fiches technique(PDF) 3 Page - Analog Devices |
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AD8383ACPZ Fiches technique(HTML) 3 Page - Analog Devices |
3 / 16 page AD8383 Rev. 0 | Page 3 of 16 SPECIFICATIONS Table 1. @25°C, AVCC = 15.5 V, DVCC = 3.3 V, TMIN = 0°C, TMAX = 75°C, VFS = 5 V, VREFLO = V1 = V2 = 7 V, unless otherwise noted Parameter Conditions Min Typ Max Unit VIDEO DC PERFORMANCE1 TMIN to TMAX, DAC Code 450 to 800 VDE –7.5 +7.5 mV VCME –3.5 +3.5 mV REFERENCE INPUTS V1, V2 Range 5 AVCC – 4 V V2 to V1 Range –0.25 V V1 Input Current +0.2 µA V2 Input Current –7.5 µA VREFHI Range VREFHI ≥ VREFLO VREFLO AVCC V VREFLO Range VREFHI ≥ VREFLO V1 – 0.5 AVCC – 1.3 V VREFHI Input Resistance To VREFLO 20 kΩ VREFLO Bias Current –0.2 µA VREFHI Input Current 125 µA VFS Range2 0 5.5 V RESOLUTION Coding Binary 10 Bits DIGITAL INPUT CHARACTERISTICS Maximum Input Data Update Rate3 100 Ms/s CLK to Data Setup Time 0 ns CLK to STSQ Setup Time 1 ns CLK to XFR Setup Time 1 ns CLK to Data Hold Time 3 ns CLK to STSQ Hold Time 3 ns CLK to XFR Hold Time 3 ns CLK High Time 3 ns CLK Low Time 2.5 ns CIN 3 pF IIH 0.05 µA IIL 0.6 µA IIL, CLK 1.2 µA VIH 2 V VIL 0.8 V VTH 1.5 V VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing AVCC – VOH, VOL – AGND 1.1 1.3 V CLK to VID Delay4 50% of VIDx 10.0 12.0 14.0 ns INV to VID Delay 50% of VIDx 10.4 12.4 14.4 ns Output Current 100 mA Output Resistance 22 Ω 1 VDE = Differential Error Voltage = Common-Mode Error Voltage. See section. Theory of Operation 2 VFS = 2 × (VREFHI – VREFLO). 3 Maximum input transition time (10% to 90%) = 0.8/(2f) where f is the operating CLK rate. 4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV. |
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