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FM25040-P Fiches technique(PDF) 8 Page - List of Unclassifed Manufacturers

No de pièce FM25040-P
Description  4Kb FRAM Serial Memory
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FM25040-P Fiches technique(HTML) 8 Page - List of Unclassifed Manufacturers

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Ramtron
FM25040
11 May 2000
8/14
Data Retention and Endurance
Data
retention
is
specified
in
the
electrical
specifications below. For purposes of clarity, this
section contrasts the retention and endurance of
FRAM with EEPROM. The retention performance of
FRAM is very comparable to EEPROM in its
characteristics. However, the effect of endurance
cycles on retention is different.
A
typical
EEPROM
has
a
write
endurance
specification that is fixed. Surpassing the specified
level of cycles on an EEPROM usually leads to a
hard memory failure. By contrast, the effect of
increasing cycles on FRAM produces an increase in
the soft error rate. That is, there is a higher likelihood
of data loss but the memory continues to function
properly. A hard failure would not occur by simply
exceeding the endurance specification; simply a
reduction in data retention reliability. While enough
cycles would cause an apparent hard error, this is
simply a very high soft error rate. This characteristic
makes it problematic to assign a fixed endurance
specification.
Endurance is a soft specification. Therefore, the user
may operate the device with different levels of
endurance cycling for different portions of the
memory. For example, critical data needing the
highest reliability level could be stored in memory
locations that receive comparatively few cycles. Data
with shorter-term use could be located in an area
receiving many more cycles. A scratchpad area,
needing little if any retention can be cycled until there
is virtually no retention capability remaining. This
would occur several orders of magnitude above the
endurance spec.
Internally, a FRAM operates with a read and restore
mechanism similar to a DRAM. Therefore, endurance
cycles are applied for each access: read or write. The
FRAM architecture is based on an array of rows and
columns. Each access causes a cycle for an entire
row.
Therefore,
data
locations
targeted
for
substantially differing numbers of cycles should not
be located within the same row. In the FM25040,
there are 64 rows each 64 bits wide. Each 8 bytes in
the address mark the beginning of a new row.
Figure 9 Memory Read
Figure 8 Memory Write


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