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74V2G70CTR Fiches technique(PDF) 1 Page - STMicroelectronics |
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74V2G70CTR Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 13 page 1/13 December 2001 s HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 1 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V s FUNCTION COMPATIBLE WITH 74 SERIES 74 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V2G74 is an advanced high-speed CMOS SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. A signal on the D INPUT is transfered to the Q and Q OUTPUTS during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. 74V2G74 SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-8L 74V2G70STR SOT323-8L 74V2G70CTR SOT23-8L SOT323-8L |
Numéro de pièce similaire - 74V2G70CTR |
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Description similaire - 74V2G70CTR |
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