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ADC082S021EVAL Fiches technique(PDF) 2 Page - National Semiconductor (TI) |
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ADC082S021EVAL Fiches technique(HTML) 2 Page - National Semiconductor (TI) |
2 / 19 page Block Diagram 20124807 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description ANALOG I/O 5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to V A. DIGITAL I/O 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 7 DOUT Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6 DIN Digital data input. The ADC082S021’s Control Register is loaded through this pin on rising edges of the SCLK pin. 1CS Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. POWER SUPPLY 2V A Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND witha1µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 3 GND The ground return for the analog supply and signals. www.national.com 2 |
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