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TSEV81102G0TPZR3 Fiches technique(PDF) 4 Page - ATMEL Corporation

No de pièce TSEV81102G0TPZR3
Description  DMUX 8-/10-bit 2 GHz 1:4/8
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Fabricant  ATMEL [ATMEL Corporation]
Site Internet  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TSEV81102G0TPZR3 Fiches technique(HTML) 4 Page - ATMEL Corporation

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TS81102G0
2105C–BDC–11/03
Functional
Description
The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology fea-
turing a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be
processed at the DMUX output.
The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1
Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio.
The TS81102G0 is able to process 8 or 10-bit data flows.
The input clock can be an ECL differential signal or single-ended DC coupled signal. Moreover
it can be a DataReady or DataReady/2 clock.
The input digital data must be an ECL differential signal.
The output signals (Data Ready, digital data and reference voltage) are adjustable with
VplusD independent power supply. Typical output modes are ECL, PECL or TTL.
The Data Ready output is a differential signal. The digital output data and reference voltages
are single-ended signals.
The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the
user to re-synchronize the output port selection and to minimize loss of data that could occur
within the DMUX.
A delay adjust cell is available to ensure a good phase between the DMUX’ input clock and
input data.
Another delay adjust cell is available to control the ADCss sampling instant alignment, in case
of the ADCs interleaving.
A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test
sequence is very useful for testing the DMUX at first use.
A fine tuning of the output swing is also available.
The TS81102G0 can be used with the following Atmel ADCs:
TS8388B(F/FS/GL), 8-bit 1 Gsps ADC
TS83102G0B, 10-bit 2 Gsps ADC


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