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TSB14AA1AT Fiches technique(PDF) 9 Page - Texas Instruments |
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TSB14AA1AT Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 37 page 1–4 1.5 Terminal Descriptions TERMINAL TYPE I/O DESCRIPTION NAME NO. TYPE I/O DESCRIPTION CLK_SEL0 46 CMOS I Clock select 0. If this terminal is set to low (0) then the speed is 98.304 Mbps. If this terminal is set to high (1) the speed is 49.152 Mbps. To operate at 100 Mbps requires an input clock of 98.304 MHz. To operate at 49.152 Mbps requires an input clock of 49.152 MHz. CLK_SEL1 47 CMOS I Clock select 1. CLK_SEL1 must be tied to ground during normal operation. CTL0, CTL1 7, 8 CMOS I/O Control I/O. These are bidirectional signals that communicate between the TSB14AA1A and the link layer that controls the passage of information between the two devices. D0, D1 10, 12 CMOS I/O Data I/O. These are bidirectional information signals that communicate the data between the TSB14AA1A and the link layer controller. EN 38 Supply I Enable on-chip regulator. This active low pin enables the 1.8 V on–chip regulator. EX_ID0 19 CMOS I External ID 0. The state of this pin sets the value of bit 0 of the PHYSICAL_ID field in the NODE ID Register upon hardware or SWHRST reset. The register bit may be modified by software. EX_ID1 20 CMOS I External ID 1. The state of this pin sets the value of bit 1 of the PHYSICAL_ID field in the NODE ID register upon hardware or SWHRST reset. The register bit may be modified by software. EX_ID2 21 CMOS I External ID 2. The state of this pin sets the value of bit 2 of the PHYSICAL_ID field in the NODE ID register upon hardware or SWHRST reset. The register bit may be modified by software. EX_ID3 22 CMOS I External ID 3. The state of this pin sets the value of bit 3 of the PHYSICAL_ID field in the NODE ID register upon hardware or SWHRST reset. The register bit may be modified by software. EX_ID4 23 CMOS I External ID 4. The state of this pin sets the value of bit 4 of the PHYSICAL_ID field in the NODE ID register upon hardware or SWHRST reset. The register bit may be modified by software. EX_ID5 24 CMOS I External ID 5. The state of this pin sets the value of bit 5 of the PHYSICAL_ID field in the NODE ID register upon hardware or SWHRST reset. The register bit may be modified by software. EX_PR0 13 CMOS I External priority 0. The state of this pin sets the value of bit 0 of the PRIORITY field in the PRIORITY register upon hardware or SWHRST reset. The register bit may be modified by software. EX_PR1 14 CMOS I External priority 1. The state of this pin sets the value of bit 1 of the PRIORITY field in the PRIORITY register upon hardware or SWHRST reset. The register bit may be modified by software. EX_PR2 15 CMOS I External priority 2. The state of this pin sets the value of bit 2 of the PRIORITY field in the PRIORITY register upon hardware or SWHRST reset. The register bit may be modified by software. EX_PR3 16 CMOS I External priority 3. The state of this pin sets the value of bit 3 of the PRIORITY field in the PRIORITY register upon hardware or SWHRST reset. The register bit may be modified by software. GND 4, 18, 28, 32, 34, 44 Supply Ground voltage reference IDS 9 CMOS I Invert data strobe. When this pin is set low, the TDATA, TSTRB, RDATA, RSTRB, OCDOE, and TDOE pins operate normally (i.e., true). When this pin is set high, these six pins are inverted. LINKON 2 CMOS O Link-On output. This pin notifies the LLC to power-up and become active. LINKON is a square-wave signal with a frequency between 4 and 8 MHz when active. LINKON is otherwise driven low, except during a hardware reset when it is high impedance. LINKON is activated if the LPS is inactive (LLC inactive) and when the PHY receives a link-on PHY packet addressed to this node. Once activated, LINKON will continue active until the LPS becomes active (LLC active). The PHY also deasserts (low) LINKON when a bus-reset occurs. |
Numéro de pièce similaire - TSB14AA1AT |
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Description similaire - TSB14AA1AT |
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