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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SLG46400 Fiches technique(PDF) 59 Page - Dialog Semiconductor |
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SLG46400 Fiches technique(HTML) 59 Page - Dialog Semiconductor |
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59 / 95 page  000-0046400-109 Page 53 of 89 SLG46400 16.0 Clock Management The RC Oscillator (RC OSC) of the SLG46400 provides an internal clock to the ADC, PWM/DCMP, Delays and Counter logic cells. It has a frequency range of 27kHz – 10MHz which can be adjusted through the RCO_freq_cont registers <586:583>. 16.1 Clock Management Functional Diagram 16.2 RC OSC Power Down Control The power down source for the RC OSC logic cell is selected by reg <815:814> (shared with the DCMP and ADC). When reg <815:814> = ‘11’, the power down control comes from the connection matrix. The SHARED PD signal should be LOW in order to turn on the RC OSC. This signal has the highest priority and if the RC OSC is off, no other blocks of registers will be available. 16.3 RC OSC Dividers Control RC OSC dividers output to matrix can be controlled through setting the reg <816>. When the reg <816> = ‘0’ than the deviders output to matrix is allowed. When the reg <816> = ‘1’ than the deviders output to matrix will be disabled if no other blocks use them (CNT, DLY and so on). 16.4 Ring Oscillator and External Clock from PIN 5 In addition to the internal RC Oscillator, GreenPAK2 has an internal Ring Oscillator that operates on a single fixed frequency that ranges between 2 MHz and 27 MHz. This value varies from chip to chip and with VDD and temperature. To enable this function reg<587> and reg<670> should be set to ‘1’. It is also possible to use the external clock signal from PIN5 as the source. To enable the external clock from PIN5, configure reg<587> = ’1’ and reg<670> = ’0’. In either case, the Ring Oscillator or external clock signal will feed the ADC through an internal /64 divider, the PWM/DCMP blocks and CNT/DLY/FSM blocks through /4, /8, and /12 frequency dividers, and the matrix through /4 and /12 frequency dividers. Direct connection to matrix is not possible (CNT/DLY/FSM blocks and matrix will be fed from the internal RC Oscillator without dividers). Figure 30. Clock Management Functional Diagram reg <586:583> reg <582> Force OSC Frequency select reg <815:814> To Connection Matrix <26> RC Oscillator PD Select Power Down Connection Matrix output <3> PD Selection Control 1 0 External Clock Select reg <587> 1 0 en reg <670> Ring Osc. PIN 5 RCOSC To DLY/CNT/FSM /64 To ADC To PWM/DCMP /4 /8 /12 To DLY/CNT/FSM To Connection Matrix 27 To DLY/CNT/FSM To Connection Matrix 28 To DLY/CNT/FSM External Clock from PIN 5 when reg <805> = 1 CKOSC EXT. CLK SHARED PD |
Numéro de pièce similaire - SLG46400 |
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Description similaire - SLG46400 |
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