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SLG46400 Fiches technique(PDF) 51 Page - Dialog Semiconductor |
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SLG46400 Fiches technique(HTML) 51 Page - Dialog Semiconductor |
51 / 95 page 000-0046400-109 Page 45 of 89 SLG46400 13.7 CNT2 as a Finite State Machine (FSM0) CNT2 can be used as a 14-bit Finite State Machine, which has features for UP/DOWN/KEEP control and loading data select. • When UP/DOWN = “1“: CNT2 is in up-counting mode, after POR or reset, the Q value will count from 0 to 16383, then the N is loaded (d <13:0>) and the Q value count from loaded data N to 16383. When Q is equal to 16383, OUT generates a single clock cycle pulse as shown in Figure (FSM Behavior). • When UP/DOWN = “0“: CNT2 is in down-counting mode, the Q value will count from the loaded data value of N (based on reg<651:638> + 1) to 0. When Q is equal to 0, OUT generates a single clock cycle pulse as shown in Figure (FSM Behavior). • When KEEP = “1“: Q will stay at its current value. • When DLY IN has a transition (edge mode is dependent on reg<653:652>), a narrow pulse signal will be generated which will reset the CNT2 state to “0“. • For FSM operation, the Reset Source (rst_src_sel) should be set to Edge Detect in Counter Mode and user will be able to select rising, falling, or both edge (if resetting is needed), or tie reset input to ground (if resetting is not needed). • LOAD function is synchronous to Counter’s clock signal. For LOAD event to happen there should be a rising edge on the clock input of the FSM and LOAD node should be HIGH. 13.8 FSM0 (CNT2) Functional Diagram Figure 18. FSM0 (CNT2) Functional Diagram Figure 19. FSM0 Behavior FSM0 (CNT2) Counter2_end CLK_IN LOAD UP/DOWN DLY IN From Connection Matrix output <13> OUT Q<7:0> KEEP 01 00 ADC <7:0> 11 10 S2P<7:0> reg <752:751> To Connection Matrix input <31> From Connection Matrix output <14> From Connection Matrix output <20> From Connection Matrix output <12> rst_src_sel output_src_sel CNT2_force clk_is in2_edge_mode_sel reg <653:652> reg <637:635> reg <633> reg <634> reg <632> reg <651:638> d<13:0> Q4FSM0 <7:0> To PWM/DCMP reg <651:638> DATA IN * : $% < 68 7 3 4 I 3 4 3 4 3 4 > > > > I I * : $% < 68 7 3 4 |
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