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SLG46200 Fiches technique(PDF) 46 Page - Dialog Semiconductor |
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SLG46200 Fiches technique(HTML) 46 Page - Dialog Semiconductor |
46 / 69 page 000-0046200-124 Page 41 of 64 SLG46200 17.0 Delay Cells (DLY) There are three Delay Cells in the SLG46200. The time delay cells can be cascaded with one another to achieve longer time delays. Each delay cell can be triggered from a rising edge transition, a falling edge transition, or a transition in either direction. The clock frequency and counter data are used to set the output delay to a value between 0.5 μs to 380ms (4.5s for DLY1). Each time delay cell's input and output can be sourced from any user defined signal in the SLG46200. DLY1 is shared with the PWM while DLY2 is shared with S2P in parallel to serial mode. Figure 26. Delay Cells - Rising Edge Figure 27. Delay Cells - Falling Edge Figure 28. Delay Cells - Rising and Falling Edge Dly_out Rising Edge Delay Time Dly_in Pulse Width Dly_out Falling Edge Delay Time Dly_in Pulse Width Dly_out Falling Edge Delay Time Dly_in Pulse Width Rising Edge Delay Time |
Numéro de pièce similaire - SLG46200 |
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Description similaire - SLG46200 |
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