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T6B70BF Datasheet(Fiches technique) 5 Page - Toshiba Semiconductor

Numéro de pièce T6B70BF
Description  TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
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T6B70BF
2003-03-13
5
(3)
Function description and timing chart of the sending block
When modulation control input ( SCTL ) is in High-level, pseudo sine wave output is held at 0° of
the phase angle of pseudo sine wave. When modulation control input changes from High-level to
Low-level, the pseudo sine wave output (SOUT+) starts from −90° (SOUT− starts from +90°).
In this case, the time which takes to turn ON is as follows.
td (ON) < 500 ns
When modulation control input changes from Low-level to High-level, the phase angle is forcibly
held at 0°, regardless of the phase of the pseudo sine wave output. (the pseudo sine wave output is
stopped). In this case, the time which takes to turn OFF is as follows.
td (OFF) < 1 µs
(4)
Function description and timing chart of the receiving block
When it is ready to receive amplifier input signal, the time T (DET) which takes to change from
High to Low at DOUT pin is within the time which 9 to 15 waves to pass. In this case, one wave is
referenced to 16 Fosc clocks. The time width is determined by the internal clock and amplifier input
signal. The timings of the internal clock and internal detection signal in the majority logic circuit are
synchronous with each other. When input signals with the cycle, which is within the range specified
by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority
rule).
Note 1: Any communication protocol is used, however, it takes 15 carrier waves to pass when the signal changes its
state.
DOUT
T (DET)
T (DET)
Amplifier input
td (ON)
SCTL
SOUT+ pseudo sine wave output
(SOUT− output pin has the
opposite polarity)
td (OFF)




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