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IDT72V36104 Fiches technique(PDF) 2 Page - Integrated Device Technology |
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IDT72V36104 Fiches technique(HTML) 2 Page - Integrated Device Technology |
2 / 36 page COMMERCIALTEMPERATURERANGE IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2 2 PIN CONFIGURATION TQFP (PK128-1, order code: PF) TOP VIEW W/ RA CLKB 4677 drw02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ENA CLKA GND A35 A34 A33 A32 Vcc A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/ FWFT GND A22 Vcc A21 A20 A19 A18 GND A17 A16 A15 A14 A13 Vcc A12 GND A11 A10 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 PRS2/RT2 Vcc B35 B34 B33 B32 RTM GND B31 B30 B29 B28 B27 B26 Vcc B25 B24 BM GND B23 B22 B21 B20 B19 B18 GND B17 B16 Vcc B15 B14 B13 B12 GND B11 B10 INDEX SIZE DESCRIPTION The IDT72V3684/72V3694/72V36104 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are mono- lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchro- nous control. Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers’ width matches the selected Port B bus width. , |
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