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74F841 Fiches technique(PDF) 7 Page - NXP Semiconductors |
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74F841 Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product data 74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 2004 Jan 23 7 AC ELECTRICAL CHARACTERISTICS for 74F841/74F842 LIMITS Tamb = +25 °C Tamb = 0 °C to +70 °C SYMBOL PARAMETER TEST VCC = +5.0 V VCC = +5.0 V ± 10% UNIT CONDITION CL = 50 pF; RL = 500 Ω CL = 50 pF; RL = 500 Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay Dn to Qn 74F841 Waveform 1, 2 2.0 2.5 4.0 4.5 7.5 7.5 2.0 2.5 8.0 8.0 ns tPLH tPHL Propagation delay LE to Qn 74F841 Waveform 1, 2 4.5 4.0 6.5 6.0 9.5 9.0 4.0 3.5 10.0 9.5 ns tPLH tPHL Propagation delay Dn to Qn 74F842 Waveform 1, 2 3.5 3.0 5.5 5.0 8.5 8.0 4.5 4.0 9.0 8.5 ns tPLH tPHL Propagation delay LE to Qn 74F842 Waveform 1, 2 5.0 4.5 7.0 6.5 10.0 9.0 3.0 3.0 10.5 9.5 ns tPZH tPZL Output enable time HIGH or LOW-level OE to Qn or Qn Waveform 4 Waveform 5 2.5 4.0 4.5 6.0 8.0 9.5 2.0 3.0 8.5 10.5 ns tPHZ tPLZ Output disable time HIGH or LOW-level OE to Qn or Qn Waveform 4 Waveform 5 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns AC SET-UP REQUIREMENTS for 74F841/74F842 LIMITS Tamb = +25 °C Tamb = 0 °C to +70 °C SYMBOL PARAMETER TEST VCC = +5.0 V VCC = +5.0 V ± 10% UNIT CONDITION CL = 50 pF; RL = 500 Ω CL = 50 pF; RL = 500 Ω MIN TYP MIN MAX ts(H) ts(L) Set-up time, HIGH or LOW Dn to LE Waveform 3 0.0 0.0 – – 1.0 1.0 – – ns th(H) th(L) Hold time, HIGH or LOW Dn to LE 74F841 Waveform 3 2.5 3.0 – – 3.0 4.0 – – ns tw(H) LE pulse width, HIGH Waveform 3 3.5 – 4.0 – ns th(H) th(L) Hold time, HIGH or LOW Dn to LE 74F842 Waveform 3 3.0 3.5 – – 3.5 4.5 – – ns tw(H) LE pulse width, HIGH Waveform 3 3.0 – 3.0 – ns |
Numéro de pièce similaire - 74F841 |
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Description similaire - 74F841 |
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